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Reduced-complexity binary-weight-coded associative memories

Associative memories retrieve stored information given partial or erroneous input patterns. Recently, a new family of associative memories based on Clustered-Neural-Networks (CNNs) was introduced that can store many more messages than classical Hopfield-Neural Networks (HNNs). In this paper, we propose hardware architectures of such memories for partial or erroneous inputs. The proposed architectures eliminate winner-take-all modules and thus reduce the hardware complexity by consuming 65% fewer FPGA lookup tables and increase the operating frequency by approximately 1.9 times compared to that of previous work.

@inproceedings{JarOniGriGro20135,
  author = {Hooman Jarollahi and Naoya Onizawa and
Vincent Gripon and Warren J. Gross},
  title = {Reduced-complexity binary-weight-coded
associative memories},
  booktitle = {Proceedings of International Conference
on Acoustics, Speech, and Signal Processing},
  year = {2013},
  pages = {2523--2527},
  month = {May},
}