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Algorithm and Architecture for a Low-Power Content-Addressable Memory Based on Sparse-Clustered Networks

H. Jarollahi, V. Gripon, N. Onizawa and W. J. Gross, "Algorithm and Architecture for a Low-Power Content-Addressable Memory Based on Sparse-Clustered Networks," in Transactions on Very Large Scale Integration Systems, Volume 27, Number 2, pp. 375--387, 2016.

We propose a low-power content-addressable memory (CAM) employing a new algorithm for associativity between the input tag and the corresponding address of the output data. The proposed architecture is based on a recently developed sparse clustered network using binary connections that on-average eliminates most of the parallel comparisons per- formed during a search. Therefore, the dynamic energy con- sumption of the proposed design is significantly lower compared with that of a conventional low-power CAM design. Given an input tag, the proposed architecture computes a few possibilities for the location of the matched tag and performs the comparisons on them to locate a single valid match. TSMC 65-nm CMOS tech- nology was used for simulation purposes. Following a selection of design parameters, such as the number of CAM entries, the energy consumption and the search delay of the proposed design are 8%, and 26% of that of the conventional NAND architecture, respectively, with a 10% area overhead. A design methodology based on the silicon area and power budgets, and performance requirements is discussed.

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Bibtex
@article{JarGriOniGro2016,
  author = {Hooman Jarollahi and Vincent Gripon and
Naoya Onizawa and Warren J. Gross},
  title = {Algorithm and Architecture for a Low-Power
Content-Addressable Memory Based on Sparse-Clustered
Networks},
  journal = {Transactions on Very Large Scale
Integration Systems},
  year = {2016},
  volume = {27},
  number = {2},
  pages = {375--387},
}




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