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A Low-Power Content-Adressable-Memory Based on Clustered-Sparse-Networks

H. Jarollahi, V. Gripon, N. Onizawa and W. J. Gross, "A Low-Power Content-Adressable-Memory Based on Clustered-Sparse-Networks," in Proceedings of 24th International Conference on Application-specific Systems, Architectures and Processors, pp. 642--653, June 2013.

A low-power Content-Addressable-Memory (CAM) is introduced employing a new mechanism for associativity between the input tags and the corresponding address of the output data. The proposed architecture is based on a recently developed clustered-sparse-network using binary-weighted connections that on-average will eliminate most of the parallel comparisons performed during a search. Therefore, the dynamic energy consumption of the proposed design is significantly lower compared to that of a conventional low-power CAM design. Given an input tag, the proposed architecture computes a few possibilities for the location of the matched tag and performs the comparisons on them to locate a single valid match. A 0.13 um CMOS technology was used for simulation purposes. The energy consumption and the search delay of the proposed design are 9.5%, and 30.4% of that of the conventional NAND architecture respectively with a 3.4% higher number of transistors.

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Bibtex
@inproceedings{JarGriOniGro20136,
  author = {Hooman Jarollahi and Vincent Gripon and
Naoya Onizawa and Warren J. Gross},
  title = {A Low-Power Content-Adressable-Memory Based
on Clustered-Sparse-Networks},
  booktitle = {Proceedings of 24th International
Conference on Application-specific Systems,
Architectures and Processors},
  year = {2013},
  pages = {642--653},
  month = {June},
}




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