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H. Jarollahi, N. Onizawa, V. Gripon, N. Sakimura, T. Sugibayashi, T. Endoh, H. Ohno, T. Hanyu et W. J. Gross, "A NonVolatile Associative MemoryBased ContextDriven Search Engine Using 90 nm CMOS MTJHybrid LogicinMemory Architecture," dans Journal on Emerging and Selected Topics in Circuits and Systems, Volume 4, pp. 460474, 2014.
Manuscrit.
2011

We study an indexing architecture to store and search in a database of highdimensional vectors from the perspective of statistical signal processing and decision theory. This architecture is composed of several memory units, each of which summarizes a fraction of the database by a single representative vector. The potential similarity of the query to one of the vectors stored in the memory unit is gauged by a simple correlation with the memory unit’s representative vector. This representative optimizes the test of the following hypothesis: the query is independent from any vector in the memory unit vs. the query is a simple perturbation of one of the stored vectors. Compared to exhaustive search, our approach finds the most similar database vectors significantly faster without a noticeable reduction in search quality. Interestingly, the reduction of complexity is provably better in highdimensional spaces. We empirically demonstrate its practical interest in a largescale image search scenario with offtheshelf stateoftheart descriptors.
Bibtex@article{IscFurGriRabJé2017,
author = {Ahmet Iscen and Teddy Furon and Vincent
Gripon and Michael Rabbat and Hervé Jégou},
title = {Memory vectors for similarity search in
highdimensional spaces},
journal = {IEEE Transactions on Big Data},
year = {2017},
pages = {113},
}

Bibtex@article{PasGriMerPasRab2016,
author = {Bastien Pasdeloup and Vincent Gripon and
Grégoire Mercier and Dominique Pastor and Michael
Rabbat},
title = {Characterization and inference of weighted
graph topologies from observations of diffused
signals},
journal = {IEEE Transactions on Signal and
Information Processing over Networks},
year = {2016},
note = {Submitted to},
}

We study various models of associative memories with sparse information, i.e. a pattern to be stored is a random string of 0s and 1s with about logN 1s, only. We compare different synaptic weights, architectures and retrieval mechanisms to shed light on the influence of the various parameters on the storage capacity.
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Bibtex@article{GriHeuLöVer2016,
author = {Vincent Gripon and Judith Heusel and
Matthias Löwe and Franck Vermet},
title = {A Comparative Study of Sparse Associative
Memories},
journal = {Journal of Statistical Physics},
year = {2016},
volume = {164},
pages = {105129},
}

Associative memories are datastructures that allow retrieval of previously stored messages given part of their content. They thus behave similarly to human brain’s memory that is capable, for instance, of retrieving the end of a song given its beginning. Among different families of associative memories, sparse ones are known to provide the best efficiency (ratio of the number of bits stored to that of bits used). Recently, a new family of sparse associative memories achieving almostoptimal efficiency has been proposed. Their structure induces a direct mapping between input messages and stored patterns. Nevertheless, it is well known that nonuniformity of the stored messages can lead to dramatic decrease in performance. In this work, we show the impact of nonuniformity on the performance of this recent model and we exploit the structure of the model to improve its performance in practical applications where data is not necessarily uniform. In order to approach the performance of networks with uniformly distributed messages presented in theoretical studies, twin neurons are introduced. To assess the adapted model, twin neurons are used with realworld data to optimize power consumption of electronic circuits in practical testcases.
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Bibtex@article{BogGriSegHei2016,
author = {Bartosz Boguslawski and Vincent Gripon and
Fabrice Seguin and Frédéric Heitzmann},
title = {Twin Neurons for Efficient RealWorld Data
Distribution in Networks of Neural Cliques.
Applications in Power Management in Electronic
circuits},
journal = {IEEE Transactions on Neural Networks and
Learning Systems},
year = {2016},
volume = {27},
number = {2},
pages = {375387},
}

An extension to a recently introduced architecture of cliquebased neural networks is presented. This extension makes it possible to store sequences with high eff i ciency. To obtain this property, network connections are provided with orientation and with f l exible redundancy carried by both spatial and temporal redundancy, a mechanism of anticipation being introduced in the model. In addition to the sequence storage with high efficiency, this new scheme also offers biological plausibility. In order to achieve accurate sequence retrieval, a double layered structure combining heteroassociation and autoassociation is also proposed.
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Bibtex@article{JiaGriBerRab2016,
author = {Xiaoran Jiang and Vincent Gripon and
Claude Berrou and Michael Rabbat},
title = {Storing sequences in binary
tournamentbased neural networks},
journal = {IEEE Transactions on Neural Networks and
Learning Systems},
year = {2016},
volume = {27},
number = {5},
pages = {913925},
}

We propose a lowpower contentaddressable memory (CAM) employing a new algorithm for associativity between the input tag and the corresponding address of the output data. The proposed architecture is based on a recently developed sparse clustered network using binary connections that onaverage eliminates most of the parallel comparisons per formed during a search. Therefore, the dynamic energy con sumption of the proposed design is significantly lower compared with that of a conventional lowpower CAM design. Given an input tag, the proposed architecture computes a few possibilities for the location of the matched tag and performs the comparisons on them to locate a single valid match. TSMC 65nm CMOS tech nology was used for simulation purposes. Following a selection of design parameters, such as the number of CAM entries, the energy consumption and the search delay of the proposed design are 8%, and 26% of that of the conventional NAND architecture, respectively, with a 10% area overhead. A design methodology based on the silicon area and power budgets, and performance requirements is discussed.
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Bibtex@article{JarGriOniGro2016,
author = {Hooman Jarollahi and Vincent Gripon and
Naoya Onizawa and Warren J. Gross},
title = {Algorithm and Architecture for a LowPower
ContentAddressable Memory Based on SparseClustered
Networks},
journal = {Transactions on Very Large Scale
Integration Systems},
year = {2016},
volume = {27},
number = {2},
pages = {375387},
}

Finding correspondences between image features is a fundamental question in computer vision. Many models in literature have proposed to view this as a graph matching problem whose solution can be approximated using optimization principles. In this paper, we propose a different treatment of this problem from a neural network perspective. We present a new model for matching features inspired by the architecture of a recently introduced neural network. We show that by using popular neural network principles like maxpooling, kwinnerstakeall and iterative processing, we obtain a better accuracy at matching features in cluttered environments. The proposed solution is accompanied by an experimental evaluation and is compared to stateoftheart models.
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Bibtex@article{AboGriCop20169,
author = {Ala Aboudib and Vincent Gripon and Gilles
Coppin},
title = {A Neural Network Model for Solving the
Feature Correspondence Problem},
journal = {Lecture Notes in Computer Science},
year = {2016},
volume = {9887},
pages = {439446},
month = {September},
}

Thanks to their stateoftheart performance, deep neural networks are increasingly used for object recognition. To achieve the best results, they use millions of parameters to be trained. However, when targetting embedded applications the size of these models becomes problematic. As a consequence, their usage on smartphones or other resource limited devices is prohibited. In this paper we introduce a novel compression method for deep neural networks that is performed during the learning phase. It consists in adding an extra regularization term to the cost function of fullyconnected layers. We combine this method with Product Quantization (PQ) of the trained weights for higher savings in storage consumption. We evaluate our method on two data sets (MNIST and CIFAR10), on which we achieve significantly larger compression rates than stateoftheart methods.
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Bibtex@article{SouGriRob20169,
author = {Guillaume Soulié and Vincent Gripon and
Maëlys Robert},
title = {Compression of Deep Neural Networks on the
Fly},
journal = {Lecture Notes in Computer Science},
year = {2016},
volume = {9887},
pages = {153170},
month = {September},
}

An emerging trend in visual information processing is toward incorporating some interesting properties of the ventral stream in order to account for some limitations of machine learning algorithms. Selective attention and cortical magnification are two such important phenomena that have been the subject of a large body of research in recent years. In this paper, we focus on designing a new model for visual acquisition that takes these important properties into account.
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Bibtex@article{AboGriCop20169,
author = {Ala Aboudib and Vincent Gripon and Gilles
Coppin},
title = {A Biologically Inspired Framework for
Visual Information Processing and an Application on
Modeling BottomUp Visual Attention},
journal = {Cognitive Computation},
year = {2016},
pages = {120},
month = {September},
}

Associative memories allow the retrieval of previously stored messages given a part of their content. In this paper, we are interested in associative memories based onpartite graphs that were recently introduced. These memories are almost optimal in terms of the amount of storage they require (efficiency) and allow retrieving messages with low complexity. We propose a generic im plementation model for the retrieval algorithm that can be readily mapped to an integrated circuit and study the retrieval performance when hardware components are affected by faults. We show using analytical and simulation results that these associative memories can be made resilient to circuit faults with a minor modification of the retrieval algorithm. In one example, the memory retains 88% of its efficiency when 1% of the storage cells are faulty, or 98% when 0.1% of the binary outputs of the retrieval algorithm are faulty. When considering storage faults, the fault tolerance exhibited by the proposed associative memory can be comparable tousing a capacityachieving error correction code for protecting the stored information.
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Bibtex@article{LedGriRabGro2015,
author = {François LeducPrimeau and Vincent Gripon
and Michael Rabbat and Warren J. Gross},
title = {FaultTolerant Associative Memories Based
on cPartite Graphs},
journal = {IEEE Transactions on Signal Processing},
year = {2015},
volume = {64},
number = {4},
pages = {829841},
}

H. Jarollahi, N. Onizawa, V. Gripon, N. Sakimura, T. Sugibayashi, T. Endoh, H. Ohno, T. Hanyu et W. J. Gross, "A NonVolatile Associative MemoryBased ContextDriven Search Engine Using 90 nm CMOS MTJHybrid LogicinMemory Architecture," dans Journal on Emerging and Selected Topics in Circuits and Systems, Volume 4, pp. 460474, 2014.
This paper presents algorithm, architecture, and fabrication results of a nonvolatile contextdriven search engine that reduces energy consumption as well as computational delay compared to classical hardware and softwarebased approaches. The proposed architecture stores only associations between items from multiple search fields in the form of binary links, and merges repeated field items to reduce the memory requirements and ac cesses. The fabricated chip achievesmemory reduction and 89% energy saving compared to a classical fieldbased approach in hardware, based on contentaddressable memory (CAM). Furthermore, it achievesreduced number of clock cycles in performing search operations compared to the CAM, and five or ders of magnitude reduced number of clock cycles compared to a fabricated and measured ultra lowpower CPUbased counterpart running a classical search algorithm in software. The energy con sumption of the proposed architecture is on average three orders of magnitude smaller than that of a softwarebased approach. A magnetic tunnel junction (MTJ)based logicinmemory architec ture is presented that allows simple routing and eliminates leakage current in standby using 90 nm CMOS/MTJhybrid technologies.
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Bibtex@article{JarOniGriSakSugEndOhnHanGro2014,
author = {Hooman Jarollahi and Naoya Onizawa and
Vincent Gripon and Noboru Sakimura and Tadahiko
Sugibayashi and Tetsuo Endoh and Hideo Ohno and
Takahiro Hanyu and Warren J. Gross},
title = {A NonVolatile Associative MemoryBased
ContextDriven Search Engine Using 90 nm CMOS
MTJHybrid LogicinMemory Architecture},
journal = {Journal on Emerging and Selected Topics
in Circuits and Systems},
year = {2014},
volume = {4},
pages = {460474},
}

Associative memories retrieve stored information given partial or erroneous input patterns. A new family of associative memories based on Sparse Clustered Networks (SCNs) has been recently introduced that can store many more messages than classical HopfieldNeural Networks (HNNs). In this paper, we propose fullyparallel hardware architectures of such memories for partial or erroneous inputs. The proposed architectures eliminate winnertakeall modules and thus reduce the hardware complexity by consuming 65% fewer FPGA lookup tables and increase the operating frequency by approximately 1.9 times compared to that of previous work. Furthermore, the scaling behaviour of the implemented architectures for various design choices are investigated. We explore the effect of varying design variables such as the number of clusters, network nodes, and erased symbols on the error performance and the hardware resources.
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Bibtex@article{JarOniGriGro2014,
author = {Hooman Jarollahi and Naoya Onizawa and
Vincent Gripon and Warren J. Gross},
title = {Algorithm and Architecture of
FullyParallel Associative Memories Based on Sparse
Clustered Networks},
journal = {Journal of Signal Processing Systems},
year = {2014},
pages = {113},
}

Nous proposons une extension d'un réseau de neurones binaires récemment introduit qui permet l'apprentissage de messages parcimonieux, en grand nombre et avec une efficacité de mémorisation importante. Ce nouveau réseau est motivé à la fois par des aspects biologiques et informationels. Les règles d'apprentissage et de remémoration sont détaillées et illustrées par des résultats de simulations divers.
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Bibtex@article{AliBerGriJia2014,
author = {Behrooz Kamary Aliabadi and Claude Berrou
and Vincent Gripon and Xiaoran Jiang},
title = {Storing sparse messages in networks of
neural cliques},
journal = {IEEE Transactions on Neural Networks and
Learning Systems},
year = {2014},
volume = {25},
pages = {980989},
}

Des réseaux de neurones avec trois niveaux de parcimonie sont introduits. Le premier d’entre eux est la taille des messages, bien plus petite que le nombre de neurones des réseaux. Le second provient d’une règle de codage singulière qui agit comme une contrainte locale sur l’activité neuronale. Le troisième est le caractère creux du réseau lui même tel qu’il se présente à la fin de l’apprentissage. Bien que ce modèle proposé soit très simple, s’appuyant sur des neurones et des connexions binaires, il peut apprendre et retrouver un grand nombre de messages même en présence de nombreux effacements.
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Bibtex@article{GriBer20117,
author = {Vincent Gripon and Claude Berrou},
title = {Sparse neural networks with large learning
diversity},
journal = {IEEE Transactions on Neural Networks},
year = {2011},
volume = {22},
number = {7},
pages = {10871096},
month = {July},
}


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